VHDL中的参数化常量

当存在多个选项时,要求聚合具有本地静态选项(用于确定表达式值的代码在分析时构造。)

其他 其他

在精化(14.4.2.5对象声明)时,可以通过函数调用(表达式,9.3.4函数调用)提供常量的值表达式(6.4.2.2常量声明)或变量或信号的初始表达式。函数可能是不纯的(4。子程序和包,4.1总则,9.4.3全局静态初选,注2)。

构建 Minimal, Complete, and Verifiable example 允许演示:

library ieee;
use ieee.std_logic_1164.all;

ravenwater_mcve is
    generic (NBITS: natural := 42);
end entity;

architecture foo of ravenwater_mcve is
    impure function leftbit return std_logic_vector is
        variable retv:  std_logic_vector (NBITS - 1 downto 0) := 
                          (others => '0');
    begin
        retv(retv'LEFT) := '1';
        return retv;
    end function;
    constant NaR: std_logic_vector(NBITS - 1 downto 0) := leftbit;
    -- (NBITS - 1 => '1', others => '0');
begin
end architecture;

RESULT:
    process
    begin
        report "NaR = " & to_string(NaR);
        wait;
    end process;

    function to_string (inp: std_logic_vector) return string is
            variable image_str: string (1 to inp'length);
            alias input_str:  std_logic_vector (1 to inp'length) is inp;
    begin
        for i in input_str'range loop
            image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
        end loop;
        return image_str;
    end function;

这就产生了:

ghdl-瑞文水公司

(也许我应该为泛型常量使用较小的默认值。)