VHDL代码:转换std_logic_vector的类型转换非法

我试图将行中的值相乘:

Q<=无符号(reg_output)或(无符号(被乘数)和无符号(shifted_lsb)*“0010”);

注意:我知道被乘数是std_logic_vector,我这样做是为了通过if进行比较。

每次编译时都会出现错误: 从ieee.std_logic_1164.std_logic到ieee.NUMERIC_std的类型转换非法。UNSIGNED(非数值到数组)。

下面是我的代码:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; 
entity shiftaddr is
 port(
 clk, clear : in std_logic;
 multiplicand: in std_logic_vector(3 downto 0);
 reg_output: in unsigned(7 downto 0);
 shifted_lsb: in std_logic;
 Q: out unsigned(7 downto 0) );
end shiftaddr;

architecture arch of shiftaddr is
 signal temp: std_logic_vector(3 downto 0);
begin

 shift: process(clk,clear,multiplicand, shifted_lsb,reg_output) --Define a process and state the inputs


begin

if (clk = '0') then
 Q <= reg_output;
end if;

if (clk = '1') then


    if (multiplicand(0) = '1') then Q <= (reg_output);
    end if;

    if (multiplicand(1) = '1') then 
    Q<= unsigned(reg_output) or (unsigned(multiplicand) and unsigned(shifted_lsb)*"0010");
    end if;
end if;

 end process;
end arch;

我该如何解决这个问题?谢谢