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在verilog中自动增加案例状态

fsm verilog

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FabienM · 技术社区 · 7 年前

目前我定义了一些verilog宏:

`define WB_READ(READ_ADDR) \
        begin \
        wb_addr_o <= UART_DIV;\
        wb_stb_o  <= 1'b1; wb_cyc_o  <= 1'b1; wb_we_o <= 1'b0; end

`define WB_WRITE(WR_ADDR, WVALUE) \
        begin \
        wb_addr_o <= WR_ADDR;\
        wb_wdat_o <= WVALUE;\
        wb_stb_o  <= 1'b1; wb_cyc_o  <= 1'b1; wb_we_o <= 1'b1; end\

`define WB_NOPE \
        begin\
        wb_stb_o  <= 1'b0; wb_cyc_o  <= 1'b0; wb_we_o <= 1'b0; end

  always @(posedge clk or posedge rst)
    if(rst) begin
      count <= 8'h00; 
      wb_addr_o <= 8'h00;
      wb_wdat_o <= 8'h00;
      wb_stb_o  <= 1'b0; 
      wb_cyc_o  <= 1'b0; 
      wb_we_o   <= 1'b0; 
    end
    else begin
        case(count)
            {7'h01, 1'b1}: `WB_READ(UARD_DIV)
            {7'h02, 1'b1}: `WB_READ(UARD_DIV)
            {7'h03, 1'b1}: `WB_WRITE(UART_LCR, 8'h60)
            {7'h04, 1'b1}: `WB_WRITE(UART_DIV, 8'h01) 
            {7'h05, 1'b1}: `WB_WRITE(UART_THR, 8'h55) 
            default: `WB_NOPE
        endcase
        if (count < {7'h06, 1'b1})
            count <= count + 1;
    end

每次计数为偶数时,执行WB不可用状态,每次计数为奇数时,执行给定的命令。

有人知道如何改进这个(用宏?)为了避免它?

1 回复 | 直到 7 年前

1

FabienM 7 年前

您可以在case语句中使用一个整数值,并为每个步骤递增它。这里有一个稍微精简的代码版本,它可以满足您的需要(或者至少有一些足够接近的东西可以修复它:-)

module testcase (input logic clk,input logic rst);

enum logic [1:0] { READ,WRITE,NOP } op;
logic [7:0] count;

`define WB_READ  begin op <= READ; end
`define WB_WRITE begin op <= WRITE; end
`define WB_NOPE  begin op <= NOP; end
logic [6:0] fsm_step_number;

  always @(posedge clk or posedge rst)
    if(rst) begin
      count <= 8'h00; 
      op <= NOP;
    end
    else begin
        fsm_step_number=1;
        case(count)
            {(fsm_step_number++), 1'b1}: `WB_READ
            {(fsm_step_number++), 1'b1}: `WB_READ
            {(fsm_step_number++), 1'b1}: `WB_WRITE
            {(fsm_step_number++), 1'b1}: `WB_WRITE
            {(fsm_step_number++), 1'b1}: `WB_WRITE
            default: `WB_NOPE
        endcase
        if (count < {(fsm_step_number), 1'b1})
            count <= count + 1;
    end

    assert

endmodule