凿子3禁用发电机导线

wire instance1_io_somePort;
reg _GEN_3;                 // Want disable generation of this

my_module instance1(
  ...
  .some_port(instance1_io_somePort)
)

assign instance1_io__somePort = _GEN_3; // and this strings.

=============更新14\u 07\u 17================

问题不是关于io端口,而是关于内部

import chisel3._

class A extends Bundle {
  val in = Input(Bool())
  val out = Output(Bool())
}

class X extends Module {
  val io = IO(new Bundle {
    val A_IF = new A
  })
  val reg = RegInit(UInt(2.W), init = 0.U)


  io.A_IF.out := (reg === 2.U)

  when(io.A_IF.in === true.B){
    reg := 1.U
  }.elsewhen(io.A_IF.in === false.B){
    reg := 2.U
  }
}

object example extends App {
  Driver.execute(Array("-td", "./"), () => new X())
}

这段代码生成了一堆verilog

module X(
  input   clock,
  input   reset,
  input   io_A_IF_in,
  output  io_A_IF_out
);
  reg [1:0] reg$;
  reg [31:0] _GEN_2; // don't wanna this reg to appear
  wire  _T_7;
  wire [1:0] _GEN_0; // and this 
  wire  _T_12;
  wire  _T_15;
  wire [1:0] _GEN_1; // and this wires 
  assign io_A_IF_out = _T_7;
  assign _T_7 = reg$ == 2'h2;
  assign _GEN_0 = io_A_IF_in ? 2'h1 : reg$;
  assign _T_12 = io_A_IF_in == 1'h0;
  assign _T_15 = _T_12 & _T_12;
  assign _GEN_1 = _T_15 ? 2'h2 : _GEN_0;
`ifdef RANDOMIZE
  //chisels randomize code here
`endif
  always @(posedge clock) begin
    if (reset) begin
      reg$ <= 2'h0;
    end else begin
      if (_T_15) begin
        reg$ <= 2'h2;
      end else begin
        if (io_A_IF_in) begin
          reg$ <= 2'h1;
        end
      end
    end
  end
endmodule

我想知道,是否可以禁用生成第2代和第1代导线以及第0代reg?为什么会出现这个氏族?